In recent years, attention has been given to a wireless charging system whereby power is supplied wirelessly.
In the wireless charging, required is a high frequency power source capable of outputting AC signals (voltage, current) such as sine waves having a certain level of power.
Since a signal having high-power sine waves can be hardly generated with high efficiency, an inverter configured to generate square waves by switching operation and whereby high efficiency can be achieved with a simple circuit configuration is generally used as a high frequency power source.
In the inverter, a power MOS FET (Metal Oxide Semiconductor FET) is used as a switch element to execute switching operation, for example.
FIG. 1 is a diagram illustrating an exemplary configuration of a section configured to execute switching of an inverter in a related art.
In FIG. 1, an FET 1 has a source grounded (connected to a ground wire) and a drain connected to a terminal or a line, not illustrated, configured to switch (turn on/off) the connection with the ground wire.
Further, the FET 1 has a gate configured to be supplied with a pulse (gate pulse) output from a pulse output section 2, and the FET 1 (gate) is driven by the pulse output from the pulse output section 2.
More specifically, the FET 1 is the FET of an nMOS (negative channel MOS), and configured to be turned on when the pulse of a level H (High) is applied to the gate and to be turned off when the pulse of a level L (Low) is applied (when the pulse of the level H is not applied).
Therefore, the FET 1 performs switching operation whereby the FET 1 is turned on when the pulse output from the pulse output section 2 is the level H (High) and is turned off when the same pulse is the level L (Low).
Meanwhile, the FET 1 is needed to be a power MOS FET having a small resistance (on-resistance) between the drain and the source in order to improve efficiency of the inverter.
However, it is necessary to increase a channel width of a channel of the FET 1 in order to make the on-resistance of the FET 1 small, and as trade-off thereof, input capacitance Ciss at the gate is increased.
Therefore, input resistance at the gate of the FET 1 is large, but the input capacitance Ciss is also large. Accordingly, the FET 1 is to be a heavy capacitive load for the pulse output section 2 (driver) that outputs pulse to drive the FET 1 that has such a large input capacitance Ciss.
More specifically, when the FET 1 is turned on, a large amount of electric charge is required to charge the large input capacitance Ciss and heavy current flows. Further, when the FET 1 is turned off, a large amount of the electric charge that has been charged to the input capacitance Ciss is discharged, and heavy current flows.
Therefore, at the time of switching the FET 1, a phenomenon equivalent to filling a glass with electric charge and discharging the electric charge from the glass occurs as illustrated in FIG. 1, and a large amount of power is lost.
Such power loss at the time of switching becomes more obvious in the case of executing switching at a high speed.
Considering this, proposed is a gate driving circuit of power MOS FET in Patent Document 1, for example, whereby power loss is reduced by flowing current in a coil to accumulate energy and regenerating the energy.